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rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 1 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? description the lx1688 is a fixed frequency, dual current/voltage mode, switching regulator that provides the control function for cold cathode fluorescent lighting (ccfl). this controller can be used to drive a single lamp, but is specifically designed for multiple lamp lcd panels. the ic can be configured as a master or slave and synchronize up to 12 controllers. the lx1688 includes highly integrated universal ?pwm or dc? dim input that allows either a pwm or dc input to adjust brightness without re quiring external conditioning, since a single external capacitor cpwm can be used to integrate a pwm input. burst mode dimming is possible if the user supplies a low frequency pwm signal on the brite input and no cpwm capacitor is used. the controller utilizes mi crosemi?s patented direct drive fixed frequency topology and patented resonant lamp strike generation technique. safety and reliability features include a dual feedback control loop that permits regulation of maximum lamp strike voltage as well as lamp current. regulating maximum lamp voltage permits the designer to provide for ample worst-case lamp strike voltage while conservatively limiting maximum open circuit voltage. in addition the controller features include auto shutdown for an open or broken lamp, and a lamp fault detection with a status reporting output. to improve design flexibility the ic includes the ability to select the polarity of both the chip enable and dim (brite) inputs. also included is a switched vdd output of up to 10ma that will allow the user to power other circuitry that can be switched on and off with the inverters enable input. this preserves the micro power sleep mode with no additional components. important: for the most current data, consult microsemi ?s website: http://www.microsemi.com protected by u.s. patents 5,615,093; 5,923 ,129; 5,930,121; 6,198, 234; patents pending key features ? provision to synchronize lamp current & frequency with other controllers ? dimming with analog or digital (pwm) methods (>20:1) ? programmable fixed frequency ? adjustable power-up reset ? enable/brite polarity selection ? voltage limiting on step-up transformer secondary winding ? open lamp timeout circuitry ? switched vdd output (10ma) ? micro-amp sleep mode ? operates with 3.3v to 5v supply ? 100ma output drive capability applications / benefits ? desktop lcd monitors ? multiple lamp panels ? low ambient light displays ? high efficiency ? lower cost than conventional buck/royer inverter topologies ? improved lamp strike capability ? improved over-voltage control product highlight 12 24 13 lx1688 master fets 12 24 13 lx1688 slave fets fault 1 fault 2 ramp reset phase sync input connector lamps dimming (brite) enable brite enable fault 1 fault 2 vdd strike status strike status ch2 10.0mv m 100s ch3 10.0mv 125 hz 5% duty cycle burst 65khz run frequency simplified quad lamp inverter showing synchronized output waveforms package order info pw plastic tssop 24-pin t j ( c) m in v dd m ax v dd rohs compliant / pb-free transition dc: 0442 0 to 70 3.0v 5.5v lx1688cpw -40 to 85 3.0v 5.5v lx1688ipw note: available in tape & reel. append the lett ers ?tr? to the part number. (i.e. lx1688cpw-tr) l l x x 1 1 6 6 8 8 8 8
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 2 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? absolute maximum ratings supply voltage ( vdd_p, vdd) ................................................................................ 6.5v digital input s ................................................................................... -0.3 v to vdd +0.5v analog inputs .................................................................................. ?0.1v to vdd +0.5v digital out puts................................................................................. -0 .3v to vdd +0.5v analog output s ................................................................................ -0.1 v to vdd +0.5v maximum operating junc tion temperat ure ............................................................ 150c storage temperatur e................................................................................. -65c to 150c peak package solder reflow temp. ( 40 seconds max. expos ure) ................260c( +0.-5) note 1: exceeding these ratings could cause da mage to the device. all voltages are with respect to ground. currents are positive into, negative out of the specified terminal. thermal data pw plastic tssop 24-pin thermal resistance - junction to a mbient , ja 100 c/w junction temperature calculation: t j = t a + (p d x ja ). the ja numbers are guidelines for the thermal performan ce of the device/pc-board system. all of the above assume no ambient airflow. package pin out bepol vdd a out 2 3 4 5 6 7 8 9 10 11 12 1 23 22 21 20 19 18 17 16 15 14 13 24 vss_p brite cpor enable i_r cpwm1 cpwm2 rmp_rst pha_sync vdd_p vddsw tri_c olsns isns icomp vcomp vsns slave fault b out vss pw p ackage (top view) rohs / pb-free 100% matte tin lead finish functional pin description pin name description pin name description a out output driver a b out output driver b vss_p connects to dedicated gnd for aout and bout drivers vdd_p connects to dedicated vdd for aout and bout drivers vss connects to analog gnd vdd connects to analog vdd bepol tri-mode input pin to control the polarity of the enable and brite signal vddsw switchable vdd output controlled by enable brite analog/pwm input for brightness control tri_c connects to external capacitor c tri cpor connects an external capacitor c por to vdd and is used for setting power-up reset pulse width. olsns analog input to detect open-lamp condition enable used to enable or disable the chip isns analog input from lamp current, has built-in 300mv offset i_r connects to external resistor r i ; for bias current setting for internal oscillator icomp current error amp?s output; connects to external capacitor c icomp cpwm1 connects to external capacitor c pwm , used for integrating an external digital pwm signal for analog dimming vcomp voltage error amp?s output; connects to external capacitor c vcomp , can be used for soft-start cpwm2 connects to external capacitor c pwm , used for integrating an external digital pwm signal for analog dimming. vsns analog input from transformer output voltage rmp_rst if slave = ?0?, rmp_rst is a cmos output; if slave = ?1?, it is a cmos input that locks the ramp oscillation frequency to the master clock slave input control pin for setting the ic either in master or slave mode; ?1? for slave mode and ?0? for master mode. pha_sync if slave= ?0?, pha_sync is a cmos output; if slave = ?1?, it is a cmos input that make the a out /b out phase synchronous with the master fault digital output to indicate maximum number of lamp striking attempts has occurred without lamp ignition. p p a a c c k k a a g g e e d d a a t t a a
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 3 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? recommended operating conditions lx1688 parameter min typ max units supply voltage (v dd ,v ddp ) 3 5.5 v brite linear dc voltage range 1 2.5 v brite pwm logic signal voltage range 0 v dd v digital inputs (slave, pha_sync, rmp_rst, bepol, enable ) 0 v dd v electrical characteristics unless otherwise specified, specif ications apply over the range: t a =-40 to 85 o c, v dd (for lx1688iwp) & t a = 0 to 70 o c, v dd (for lx1688cwp), v dd_p = 3.0 to 5.5v. r i = 80kohms, c tri = 0.083f lx1688 parameter symbol test conditions min typ. max units dimmer v brite_max v bepol = v dd 2.6 2.5 conventional1 dimming brite input voltage v brite_min v bepol = v dd 0.4 0.5 v v brite_max v bepol = v ss or float 0.4 0.5 reverse dimming brite input voltage v brite_min v bepol = v ss or float 2.6 2.5 v max brightness v brt voltage v brt_full v bepol = v ss , v brite = 0.4v 1.90 2.0 2.05 v full-darkness v brt voltage v brt_dark v bepol = v ss , v brite = 2.6v 0 0.05 v isns input threshold voltage v th_iamp t a = 0 to 70 o c 150 300 450 mv isns input threshold voltage v th_iamp t a = -40 to 85 o c 150 300 550 mv brite-to-icomp propagation delay t d_brite 2 s strike and ramp generator max. number of strike before fault n fault 63 triangular wave generator analog output peak voltage v p_tri 2.3 2.5 2.6 v triangular wave generator analog output valley voltage v v_tri 0.15 0.3 0.40 v triangular wave generator oscillation frequency f _tri 7 10 13 hz max. lamp strike frequency f max_stk f max_stk = f lamp x ~2.5 150 195 khz lamp run frequency f lamp v olsns > 0.65v; vdd=5v t a = 0 to 70 o c 60 65 70 khz lamp run frequency f lamp v olsns > 0.65v; vdd=5v t a =-40 to 85 o c 57 65 70 khz lamp run frequency regulation over v dd f lamp_reg v olsns > 0.65v 4 6 % /v olsns threshold voltage v th_olsns 740 790 840 ? mv olsns hysteresis v h_olsns 540 590 640 ? mv olsns-to-icomp propagation delay t d_olsns gbnt 2 1 us fault, pha_sync, rmp_rst, logic high threshold v h v dd ? 0.5 v fault, pha_sync, rmp_rst, logic low threshold v l 0.7 1 v minimum fault-pin output current i_fault 10 15 ? ma 1conventional polarity means that the lamp brightness increases with increasing voltage on the brite pin. reverse polarity mea ns that brightness decr eases with increasing voltage 2 guaranteed but not production tested e e l l e e c c t t r r i i c c a a l l s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 4 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? electrical characteristics (continued) lx1688 parameter symbol test conditions min typ. max units strike and ramp generator (continued) minimum pha_sync-pin output current i _pha_sync v slave = 0v 10 ? ma minimum rmp_rst-pin output current i _rmp_rst v slave = 0v 10 ma minimum a_sync output pulse duty-cycle d o_async v slave = 0v 49 50 % minimum a_sync input pulse duty-cycle d i_async v slave = v dd 48 50 % minimum rmp_rst output pulse duty-cycle d o_rst v slave = 0v 10 17 % minimum rmp_rst input pulse duty-cycle d i_rst v slave = v dd 5 % output buffer output sink current i sk_outbuf v aout , bout = 1v v dd = 5.5v 100 ? ma output source current i s_outbuf v aout , bout = 4.5v v dd = 5.5v 100 ? ma output sink current i sk_outbuf v aout , bout = 1v, v dd = 3v 50 ? ma output source current i s_outbuf v aout , bout = 2v, v dd = 3v 50 ? ma output sink current i sk_outbuf v aout , bout = 1v, v dd = 5.5v 100 ? ma pwm vsns threshold voltage v th_vsns 1.2 1.25 1.3 v vcomp discharge current i d_vcomp 4 ? ma iamp transconductance g m_iamp i sns = 0.2v 100 200 500 mho vamp, iamp output source current i s_iamp v comp , i comp = 0 75 a vamp, iamp output sink current i sk_iamp v comp , i comp =v dd 75 a icomp discharge current i d_icomp 10 ? ma vamp transconductance g m_icmp v sns = 0.1v 200 500 800 mho icomp-to-output propagation delay t d_icomp 1100 ns bias voltage at pin i_r v _ir 0.95 1.05 v pin i_r max. source current i max_ir 50 a power-on reset pulse width t por c por =.1uf 31 ms minimum v ddsw sourcing current i min_vddsw (v dd ? v ddsw ) < 0.2v 10 25 ? ma v ddsw off current i off_vddsw v enable = 0.8v, v bepol = v dd v ddsw = 0v 1 15 a general operating current i dd v dd = v dd_p = 5v 5.5 8 ma output buffer operating current i dd_p v olsns = v dd = v dd_p = 5v, c a = c b = 1000pf 2 4 ma enable logic threshold v th_en 0.8 1.7 2.4 v enable threshold hysteresis v th_en 0.2 v i dd_sleep v enable = 0.8v (v bepol = v dd or float) 20 50 sleep-mode current (see table-1 for pin enable polarity) i dd_sleep v enable = 2.5v (v bepol = v dd or float) 20 50 i dd_sleep v enable = 0.8v (v bepol = v ss ) 20 300 vdd_p leakage in sleep mode i dd_sleep v enable = 2.5v (v bepol = v ss ) 20 300 a uvlo threshold v th_uvlo rising turn-on threshold 2.6 2.8 2.9 v uvlo hysteresis v h_uvlo falling turn-off hysteresis 190 mv e e l l e e c c t t r r i i c c a a l l s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 5 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? response vs wavelength i snk step response typical operating current (vdd) 3 3.5 4 4.5 5 5.5 6 -40 - 15 10 35 60 85 temperatur e (c) vdd input current (ma) vdd=5.5v vdd=3v isns input threshold voltage vs temperature 180 200 220 240 260 280 300 320 340 360 380 -40 -15 10 35 60 85 temperature (c) isns input threshold (v) vdd=5.5v vdd=3v output frequency vs temperature 56 58 60 62 64 66 68 70 -40 -15 10 35 60 85 temperature (c) output frequency (khz) vdd=5v vdd=3v under voltage lockout vs temperature 2.5 2.55 2.6 2.65 2.7 2.75 2.8 2.85 2.9 -40 -15 10 35 60 85 temperature (c) uvlo thresholds (v) turn on turn off i_r voltage vs temperature vdd=v 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 -40 - 15 10 35 60 85 temper ature ( c) i_r voltage (v) power-on-reset pulse width vs temperature vdd=5v 15 20 25 30 35 40 -40 - 15 10 35 60 85 temperatur e (c) tpor(ms) c c h h a a r r t t s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 6 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? table 1 pin bepol enable polarity dimming polarity* v dd + (hi = chip_on, low = chip_off conventional float + (hi = chip_on, low = chip_off) reverse v ss - (low = chip_on, hi = chip_off) reverse * conventional polarity means that the lamp brightness increases with increasing voltage on the brite pin. reverse polarity means that brightne ss decreases with increasing voltage operational modes controller mode controller operation input pin: olsns input pin: slave output pin: fault pin: rmp_rst pin: a_sync lamp frequency run > 0.6v vss l output: f int output: f int / 2 f int / 2 striking < 0.2v vss l output: f int output: f int / 2 ramping up / down master fault x vss h output: f int output: f int / 2 off run > 0.6v vdd l input: f ext input: f ext / 2 f ext / 2 striking < 0.2v vdd l input: f ext input: f ext / 2 ramping up / down slave fault x vdd h input: f ext input: f ext / 2 off simplified block diagram pha_sync rmp_rst slave isns vsns vcomp icomp pwr_bd fault v dd_p a out vss_p pwr_ bd brite 100k cpw 1 bepol enable vddsw polarity decode ttl buf vss vdd internal vdd vss pwr_gd 6 bit counter tri wave gen fault olsns ttl buf pwr_ bd 800mv 600mv ramp run generator output steering logic pwr_ gd fault b out 1.25v vdd + - + - 1v 1v error amp voltage comparator current comparator q q cpw 2 ignite fault tri_c 100k 100k 100k 200k 2.5 v + - 0.5 v brt 0-2v 1m 1m i_r cpor pwr_bd bias gen uvlo strike generator tff q r t pwr_ gd f int f ext /2 f ext 300mv vamp iamp lx1688 figure ? simplified block diagram b b l l o o c c k k d d i i a a g g r r a a m m
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 7 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? detailed description the lx1688 is a backlight controller specifically designed with a special feature set needed in multiple lamp desktop monitors, and other multiple lamp displays. while utilizing the same architecture as microsemi?s lx1686 controller it eliminates the synchronized digital dimming and adds, lamp ?strike? count out timer, lamp fault status output, and external clock input/output that permits multiple controllers to synchronize their output current both in frequency and phase. o peration f rom 3.3v and / or 5.0v i nput s upply the lx1688 is designed to operate and meet all specifications at 3.3v 10% to 5.0v 10%. the under voltage lockout is set at nominally 2.8v with a 190mv hysteresis. m aster /s lave c lock s ynchronization one or more controllers (up to 11) may be designated as slave controllers and receive ramp reset and phase synchronization from the desi gnated master controller. this will allow up to 12 lamps (24 with two lamps in series/controller design) to all operate in phase and frequency synchronization. this is important to prevent random interference between lamps through unpredictably changing electric and magnetic fields that will inevitably link them. the lx1688 has two independent oscillators, one for lamp strike and one for the lamp run frequency. the strike oscillator ramps the operating frequency slowly up and down when the open lamp sense input (olsns) indicates the lamp is not ignited. during this lamp strike condition the operating frequency of each ic will vary up and down as needed to strike its lamp. the controller is so designed that the master controller cloc k remains at the pre-selected frequency for fully ignited lamps even while striking. likewise the designated slave controller will not alter the frequency or phase of the master clock during its strike phase. thus each controller will vary its frequency as needed to strike its lamp then it will synchronize to the master clock frequency and phase. the tri_c wave generator (see block diagram) sets the rate of operating frequency variation during lamp strike. the tri_c generator is connect ed to a 6-bit counter that times out after 63 cycles and then latches the fault output high if the olsns input indicates no lamp current is flowing. even in the case of timeout fault the master controller clock will continue to provide synchronization to the slave controllers. when synchronizing more than one controller the ramp reset (rmp_rst), phase sync (pha_sync), and slave input/output are used. rmp_rst and pha_sync should be co nnected between all the controllers. the master controller should have its slave pin connected to vss (gnd) and the slave controllers slave input to vdd (high). bepol i nput the bepol pin is a tri-mode input that controls the polarity of the enable and brite input signals. depending on the state of this pin (vdd, floating, or vss) the controller can be set to allow active high enable with active high full brightness or active high or low enable with active low full brightness (see table 1). brite i nput (d imming i nput ) the brite input is capable of accepting either a dc voltage (> .5v to < 2.5v) or a pwm digital signal that is clamped on chip (< .5v or > 2.5v). a digital signal can either be passed unfiltered to effect pulse ?digital? dimming or filtered with a capacitor to effect analog dimming with a digital pwm signal. analog dimming methods: ? mechanical or digital potentiometer set to provide 1v to 2.5v on the wiper output. a filter cap from brite to signal ground is recommended. ? d/a converter output dir ectly connected to brite input. a r/c filter using a capacitor from the cpw1 input to ground for applications where the adc output may contain noise sufficient to modulate the brite input. ? a high frequency pwm digital logic pulse connected directly to the brite inpu t. the brightness (brt, internal node) output will be sensitive only to the pwm duty cycle, and not to the pwm signal amplitude, so long as the amplitude exceeds 2.6v for a logic high (1) and is less than .4v for a logic (0). this pulse frequency will typically be between 1khz and 100khz and will not be synchronized with the lcd video frame rate. a capacitor (cpwm) between cpw1 and cpw2 will integrate the pwm signal for use by the controller. digital dimming methods: ? low frequency pwm digital logic pulses connected directly to the brite input. as above the brightness (brt internal) will be sensitive only to the pwm duty cycle, and not to the pwm signal amplitude, so long as the amplitude exceeds 2.6v for a logic high (1) and is less than .4v for a logic (0). this pulse frequency will typically be in the range of 90-320hz. a a p p p p l l i i c c a a t t i i o o n n s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 8 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? detailed description and may or may not be externally synchronized to the lcd video frame rate. it will directly gate the signal brt. cpwm should not be used in this case. f ault p in the fault pin is a digital output that indicates that the maximum numbers of strike attempts has occurred without lamp ignition. in this condition the fault pin will go active high with typically 20ma drive capability. holding the olsns pin low (<200mv) will also force timeout and activate the fault pin. when used as a master, fault condition true does not inhibit master clock outputs pha_sync and rmp_rst. i_r p in the run mode frequency of the output is one half the internal ramp frequency, which is proportional to a bias current set by resistor ri of 80.6k. the output frequency can thus be adjusted by varying the value of ri-r, the typical range from about 50k to 100k. since there is some variation in the frequency due to change in the input supply (vdd) it is recommended that the value of ri-r be selected at the nominal input voltage. s leep m ode (enable s ignal ) and s witched vdd (vddsw) since the lx1688 can be used in portable battery operated systems, a very low po wer sleep mode is included. the ic will consume less than 10a quiescent current from both the vdd and vdd_p pins combined, when the enable pin is deactivated. the polarity of the enable pin is programmable by the bepol input (see table 1). in addition the controller provides a switched supply pin vddsw this output supplies at least 10ma at vdd .2v for external circuitry. this output can be used to power additional circuitry that can be enabled with the controller. rmp_rst and pha_sync pin timing requirement with s lave m ode o peration when the lx1688 is configured for slave mode operation, and rmp_rst and pha_sync is supplied from an external source, the signal timing should be met as outlined below. rmp_rst should be 2 times frequency of lamp frequency and duty should be 10 to 13%, and pha_sync should be generated by divide by 2 of rmp_rst signal. phase of these signals should be met the as shown, note the delay between the rmp_rst and pha_sync signals: min typ max unit t1 150 250 nsec t2 10 13 % t3 49 50 51 % tr, tf 100 nsec t3 duty is 50% of operating frequency. t2 t1 t3 bias & timing equations formula 1: triangular wave generator frequency, f tri [hz] ) 25 ( 1 f tri tri i c r = formula 2: lamp frequency (a out ?s switching frequency), f lamp [hz] 12 200 1 f lamp i r e- = formula 3: minimum current error amp bandwidth, bw iea_min [hz] 000048 . 0 b wiea_min icomp c = formula 4: minimum voltage error amp bandwidth, b wvea_min [hz] 000048 0 b wvea_min vcomp c . = formula 5: softstart time, t ss [sec] t ss vcomp c , , = 000 500 4 formula 6: minimum power-on rese t pulse width, t min_por [sec] 6 3 . 2 t min_por por c e = a a p p p p l l i i c c a a t t i i o o n n s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 9 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? application circuits vin gnd gnd pha_sync vbrite rmp_rst vin 1 2 3 4 5 6 7 8 9 10 cn1 enable c1 470nf 16v pha_sync vddsw c13 0.1uf 50v 1 2 cn2 hv1 lv1 c3 10nf 16v 10% r1 80.6k 1% c2 470nf 16v 10% pha_sync r2 47 aout 1 vss_p 2 vss 3 bepol 4 brite 5 cpor enable 7 i_r 8 cpwm1 9 cpwm2 10 rmp_rst 11 pha_sync 12 fault 13 slave 14 vsns 15 vcomp 16 icomp 17 isns 18 olsns tri_c 20 vdd_sw vdd 22 vdd_p 23 bout 24 r3 220 c11 10nf 16v 10% c9 4.7nf 16v 10% c6 82nf 16v 10% c7 100nf 16v 10% c8 2.2nf 16v 5% c10 10nf 16v 10% c5 220nf 16v 10% c4 220nf 16v 10% led1 c12 220 25v 1 2 3 4 5 6 7 8 u2 si9945aey 1 2 3 5 t1 1:75 c14 2.2pf 4 pcb r6 82 q2 bc847alt1 c15 2.2nf 50v 5% cog r8 100k 1 2 3 d1 baw56 q1 bc847alt1 r7 10k r5 39 r4 39 rmp_rst rmp_rst 1 2 3 d2 baw56 1 2 3 d3 bav99 r11 2.74k 1% r12 2.74k 1% c16 3.3nf 50v 5% cog r9 r10 1m 1k option 10% vddp vdd vddsw vdd vddp vdd + analog ground must connect to power ground at this point only 19 6 figure 1 ? schematic for lx1688 inverter module configured as master a a p p p p l l i i c c a a t t i i o o n n s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 10 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? application information a pplication example with lx1688 this section will highlight the features of lx1688 controller by showing a practical example. three identical inverter modules are connected to each other and each module drives a single lamp. one module configured as a master and two others configured as slaves. a complete schematic hooked up a a master is given in figure 1, the schematic provides all necessary functions such as high voltage feedback for regulation the peak lamp voltage, short-circuit protection, open lamp sensing and lamp current regulation needed for a typical application. the section follows with measurement waveforms and list of material of the actual modules. for more detail design procedure and circuit description please refer to application note (an-13), which is available in microsemi?s web site. i nput v oltage the lx1688 controller can operate at 3.3 to 5.0v 10%, in this application all modules were driven by the same power voltage (a constant 5.0v), which provides vdd for controllers, and input voltage for the power section. notice that vdd feeds all analog signals and vdd_p feeds only the output driver stage, these two signals should be filtered separately (figure 1). s etting lamp frequency the value of r1 determines magnitude of internal current sources that set timing parameters. equation (2) gives the relationship between lamp frequency (flamp) and (ri_r), r1 in schematic. for this application we choose r6=80.6 k ? , which results to a lamp frequency at 62.0 khz. d imming the lx1688 includes highly integrated universal ?pwm or dc? dim input that allows either a pwm or dc input without requiring external conditioning. in this application we choose digital dimming by applying a pwm signal to brite pin. all modules were driven by the same pwm signals, but notice that it is possible to dim each module quite separately. bepol pin has three different modes (see table 1), in this application it is connected to vdd which means active high enable with active high full brightness. the pwm signal can be vari ed in frequency between 48-320 hz. no capacitor be tween cpwm1 and cpwm2 is necessary. s etting m aster /s lave configuration simply connecting pin 14 to the ground for a master and to the vdd for a slave will do master and slave configuration. as shown in figure 2, module (a) configured as master and modules (b) and (c) configured as slaves. s ynchronization of f requency and p hase to synchronize the lamp frequency and phase of all modules, it is required to connect the rmp_rst pin of all the modules together and connect pha_sync pin of all the modules together. l ayout consideration by designing the layout in a proper way we can reduce the overall noise and emi for the module. the gate drivers for mosfets should have an independent loop that does n?t interface with the more sensitive analog control f unction, therefore lx1688 provides two power inputs with separate ground pins (analog/signal), vdd feeds all analog signals and vdd_p feeds only the output drivers, as shown in figure1 these two pins (pin 23, 24) are separated and filtered by r14, c2 and c7. the connection of two ground pins should be at only one point as shown in figure1. the power traces should be short and wide as possible and all periphery components such capacitors should be located as closed as po ssible to the controller. o scilloscope w aveforms p ictures the following oscilloscope waveform pictures are taken from the actual circuits and will show the operation of the modules in different modes when three identical modules are synchronized, one as a master, and two others as slaves. a a p p p p l l i i c c a a t t i i o o n n s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 11 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? typical slave applications c2 470nf 16v 10% vin gnd gnd pha_sync vbrite rmp_rst vin 1 2 3 4 5 6 7 8 9 1 0 cn 1 enable vddsw aout 1 vss_p 2 vss 3 bepol 4 brite 5 cpor 6 enable 7 i_r 8 cpwm1 9 cpwm2 10 rmp_rst 11 pha_sync 12 fault 13 slave 14 vsns 15 vcomp 16 icomp 17 isns 18 olsns tri_c 20 vdd_sw 21 vdd 22 vdd_p 23 bout 24 19 pha-sync rmp_rst r1 80.6k 1% c3 10nf 16v 10% vbrite vdd c1 470nf 16v 10% vddp r2 47 vdd vddsw led1 power output section r3 220 c11 c10 c9 c8 c7 c6 c5 c4 220nf 16v 10% c5 : 220nf 16v 10% c6 : 82nf 16v 10% c7 : 100nf 16v 10% c8 : 2.2nf 50v 5% c9 : 4.7nf 16v 10% c10-11 : 10nf 16v 10% master c2a 470nf 16v 10% vin gnd gnd pha_sync vbrite rmp_rst vin 1 2 3 4 5 6 7 8 9 10 cn1 enable vddsw aout 1 vss_p 2 vss 3 bepol 4 brite 5 cpor 6 enable 7 i_r 8 cpwm1 9 cpwm2 10 rmp_rst 11 pha_sync 12 fault 13 slave 14 vsns 15 vcomp 16 icomp 17 isns 18 olsns tri_c 20 vdd_sw 21 vdd 22 vdd_p 23 bout 24 19 pha-sync rmp_rst r1a 80.6k 1% c3a 10nf 16v 10% vbrite vdd c1a 470nf 16v 10% vddp r2a 47 vdd vddsw led1a power output section r3a 220 c11a c10a c9a c8a c7a c6a c5a c4a 220nf 16v 10% c5a: 220nf 16v 10% c6a: 82nf 16v 10% c7a: 100nf 16v 10% c8a: 2.2nf 50v 5% c9a: 4.7nf 16v 10% c10-11a: 10nf 16v 10% slave 1 vddsw r13a 100k c2b 470nf 16v 10% vin gnd gnd pha_sync vbrite rmp_rst vin 1 2 3 4 5 6 7 8 9 10 cn1 enable vddsw aout 1 vss_p 2 vss 3 bepol 4 brite 5 cpor 6 enable 7 i_r 8 cpwm1 9 cpwm2 10 rmp_rst 11 pha_sync 12 fault 13 slave 14 vsns 15 vcomp 16 icomp 17 isns 18 olsns tri_c 20 vdd_sw 21 vdd 22 vdd_p 23 bout 24 19 pha-sync rmp_rst r1b 80.6k 1% c3b 10nf 16v 10% vbrite vdd c1b 470nf 16v 10% vddp r2b 47 vdd vddsw led1b power output section r3b 220 c11b c10b c9b c8b c7b c6b c5b c4b 220nf 16v 10% c5b: 220nf 16v 10% c6b: 82nf 16v 10% c7b: 100nf 16v 10% c8b: 2.2nf 50v 5% c9b: 4.7nf 16v 10% c10-11b: 10nf 16v 10% vddsw r13b 100k slave 2 figure 2 ? schematic modules connected as a master and slave a a p p p p l l i i c c a a t t i i o o n n s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 12 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? theory of operation multiple lamp sync the figure 3 shows the sync signals (pha_sync and rmp_rst) timing relationship to gate signal aout, for the master module. aout and pha_sync running at th e same frequency and rmp_rst signal has the twice frequency. figure 3 - sync signals-timing relationship to a out ch2= a out (master), ch3=pha_sync, ch4=rmp_rst strike mode every ic includes a separate strike controller that operates from the primary oscillator; therefore the strike controller is independent of the sync signals. the following oscilloscope waveform picture is taken when the master module is on striking mode and the salves are on running mode. figure 5 - master is in striking mode while slaves are in running mode ch2= a out (master), ch3=a out (slave1), ch4=a out (slave2) output drivers the figure 4 shows the gate signals of the modules, which are operating, in running mode during digital dimming with 95% duty cycle. as shown all signals are synchr onized. the difference between each signal?s duty cycles is because each lamp has an independent control loop. a a p p p p l l i i c c a a t t i i o o n n s s figure 4 - output drivers of both master and slaves. ch2=a out (master), ch3=a out (slave1), ch4=a out (slave2)
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 13 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? theory of operation digital dimming the following oscilloscope waveforms are showing gate signals of master and slaves during digital dimming at 50% and 5% duty cycle. figure 6 - gate signals during digital dimming with 50% duty cycle ch2= a out (master), ch3=a out (slave1), ch4=a out (slave2) figure 7 - gate signals during digital dimming with 5% duty cycle ch2= a out (master), ch3=a out (slave1), ch4=a out (slave2 ) output currents figure 8 shows the output current of master and slaves during digital dimming with 5% duty cycle. the lamp currents are operating in phase and frequency synchronization. this prevents random interface between controllers and reduces emi. a a p p p p l l i i c c a a t t i i o o n n s s figure 8 - output current during digital dimming with 5% duty cycle r1= out(master) r2=iout(slave1) r3=iout(slave2) lamp current at 10ma/div
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 14 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? lx1688 module board list of material reference designator part description manufacture part number u1 backlight controller microsemi lx1688 u2 dual n-channel mosfet siliconix si9945aey q1, q2 npn transistor motorola bc847alt1 d1, d2 dual diode motorola baw56 d3 dual diode philips bav99 led1 led r1 80.6k 1% 1/16 w r2 47 ohm 5% 1/8 w r3 220 ohm 5% 1/8 w r4, r5 39 ohm 5% 1/16 w r6 82 ohm 5% 1/16 w r7 10k 5% 1/16 w r8 100k 5% 1/16 w r9 1k 5% 1/16 w r10 1 m 5% 1/16 w r11, r12 2.74k 1% 1/16 w c1, c2 470nf 16v 10% x7r 1206 c3 10nf 16v 10% 0805 novacap c4 220nf 16v 10% x7r 1206 c5 220nf 16v 20% 0805 avx 0805yc224mat2a c6 82nf 16v 10% x7r 0603 avx 0603yc823kat2a c7 100nf 16v 20% x7r avx 0603yc104mat2a c8 2.2nf 50v 10% novacap 0603b22k500nt c9 4.7nf 16v 10% x7r avx 0603yc472kat2a c10, c11 10nf 16v 10% x7r avx 0603yc103kat2a c12 220f tantalum 7343 avx c13 220pf 2kv 5% cog novacap 1206n221j202nt c14 2.2pf pcb c15 2.2nf 50v 5% cog avx 08055a222jat2a c16 3.3nf 50v 5% cog novacap 0805n332j500nt t1 low profile, high voltage xfmr, turns ratio 1:75 microsemi sge2645-1 cn1 connector, 10 pin molex 53261-1090 cn2 connector, 2 pin molex table 2 - list of material fo r lx1688 inverter module m m o o d d u u l l e e
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 15 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? package dimensions pw 24-pin thin small shrink outline (tssop) package c 1 2 3 p d e f a g h l b m seating plane m illimeters i nches dim min max min max a 0.85 0.95 0.033 0.037 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 7.70 7.90 0.303 0.311 e 4.30 4.50 0.169 0.177 f 0.65 bsc 0.025 bsc g 0.05 0.15 0.002 0.005 h ? 1.10 ? .0433 l 0.50 0.75 0.020 0.030 m 0 8 0 8 p 6.25 6.55 0.246 0.258 *lc ? 0.10 ? 0.004 * lead coplanarity note: dimensions do not include mold flash or pr otrusions; these shall not exceed 0.155mm(.0 06?) on any side. lead dimension shall not include solder coverage. m m e e c c h h a a n n i i c c a a l l s s
rangemax? lx1688 p roduction d ata s heet microsemi integrated products division 11861 western avenue, garden grove, ca. 92841, 714-898-8121, fax: 714-893-2570 page 16 copyright ? 2001 rev. 1.2, 2006-03-09 www. microsemi . com multiple lamp ccfl controller tm ? notes production data ? information contained in this document is proprietary to microsemi and is current as of publication date. this document may not be modified in any way without the express written consent of microsemi. product processing does not necessarily include testing of all parameters. microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. n n o o t t e e s s

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